1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a front-end portion having an interface function and a back-end portion containing a memory core are integrated onto separate semiconductor chips.
2. Description of Related Art
A storage capacity required for a semiconductor memory device, such as DRAM (Dynamic Random Access Memory), has been growing over years. To meet the requirement, in recent years, a memory device called multichip package, in which a plurality of memory chips is stacked, has been proposed. However, memory chips used in the multichip package are typical, stand-alone memory chips. Therefore, the memory chips each contain a front-end portion that provides an interface with an external section (which is for example a memory controller). Accordingly, an occupied space that can be allocated to a memory core in each memory chip is limited to an area that is calculated by subtracting the occupied space of the front-end portion from the total area of the chip. Therefore, it is difficult to dramatically increase the storage capacity per chip (or per memory chip).
Another problem is that even though a circuit that makes up the front-end portion is a logic circuit, the back-end portion containing a memory core is produced at the same time as the front-end portion, making it difficult to speed up a transistor of the front-end portion.
The following method is proposed as a solution to the problems that a front-end portion and a back-end portion are integrated onto separate chips, and the chips are stacked in order to make one semiconductor memory device (see Japanese Patent Application Laid-Open No. 2007-158237). According to the method, on a core chip where the back-end portion is integrated, an occupied space that can be allocated to a memory core increases. Therefore, it is possible to increase the storage capacity per chip (or per core chip). Meanwhile, an interface chip where the front-end portion is integrated can be produced in a different process from that of the memory core. Therefore, it is possible to form a circuit using a high-speed transistor. Moreover, a plurality of core chips can be allocated to one interface chip. Thus, it is possible to provide an extremely large-capacity, high-speed semiconductor memory device as a whole.
In a semiconductor device such as DRAM, an internal control signal is generated by decoding a command issued from an external controller. On the basis of the internal control signal, various operations, which for example include activation of a word line, column switch or data amplifier and the like, are performed. The timings of the operations are controlled with the use of a clock signal. Accordingly, various circuit blocks are each activated at the most appropriate timings. In one example, when a read command is issued, a column switch is then activated at a predetermined timing. After that, a data amplifier is activated at a predetermined timing. As a result, read data are read out from a memory cell array.
In recent years, for a DRAM, a Posted CAS method has been employed so that a column-related command, such as read command, is issued prior to an original issuing timing. In a DRAM that uses the Posted CAS method, after a column-related command, such as read command, is issued, an internal control signal is latched in a chip. After being delayed by a period of additive latency (AL), the internal control signal is supplied to various circuit blocks. Such latency control has been performed even in each memory chip of a stacked semiconductor device (see Japanese Patent Application Laid-Open No. 2006-277870).
However, in order for latency control to be performed in each memory chip of a stacked semiconductor device, each memory chip needs to be provided with a latency counter that counts the latency. Therefore, the problem is that the chip area of a memory chip increases.
Moreover, a clock signal needs to be supplied to each memory chip to operate the latency counter. The clock signal is very short in signal width compared with various internal control signals. Therefore, for example, when the clock signal is commonly supplied from an interface chip to a plurality of core chips, parasitic capacitance components and parasitic resistance components of a clock line could distort the waveform, possibly making it difficult to count the latency.
In particular, as in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2007-158237, in a semiconductor device of a type that transmits a signal using a through silicon via, a parasitic capacitance component of the through silicon via is relatively large. As a result, the above problems become more serious. Even when a resistance value of the through silicon via is higher than a design value for some reason, the above problems become more serious.